![]() I modified your code, to get my desired result. I just wanted to give one initial value and i wanted it to run forever. In your testbench we have to set it many times. Ld - Use was to make the counter reset to my expected value when ld=0 and again make ld=1 next cycle to start the downcount and again when downcounter value became 0, make ld=0 to reset the counter to expected value. I am trying to design a frequency divider for my project for that i needed this downcounter. When it reaches 0, the counter is automatically reloaded with d. a: CH1 2-phase counter input marker input completion. The code I showed loads the counter with the 8-bit input data ( d) when ld=1. The 1st bit in Acknowledge Counter External Input Completed is the input completion acknowledgement flag. When the input x0, the counter stops counting and when the input x1, the counter continues counting. You didn't provide a thorough description of the ld signal. Design a two-bit binary counter with a single input x. It uses the same clock for all flops of the counter: module down_counter (īy using nonblocking assignments ( <=) and driving the inputs on clk) in the testbench (as is done in the design), we also avoid race conditions in the testbench. Here is a common way to design a synchronous counter. Explain the operation of ' 2 bit synchronous counter using D flip-flop' by completing truth table for inputs/outputs or a state transition diagram. Electrical Engineering questions and answers. Every flip-flop uses a different clock signal. 7 minutes ago &0183 &32 Electrical Engineering. With all those module instance connections, you may have a simple connection bug.Īnother potential issue is a simulation race condition. Instead of designing an individual flip-flop then trying to connect them together, just design a simple counter. You should always use the highest level of abstraction to make the design easier to understand. Your code is too hard to debug because you are not designing at the proper level of abstraction. Ld function too is not working as expected, when ld=0 instead of reset counter to initial input, it stops counter and starts it once ld=0. It counts only the number of high bits from lsb + 1, if 0 is encountered next values till msb becomes x. d2=8'b11111111, then i am getting the downcounter it works properly for the above code,īut if i give some thing like d2=8'10010011, then counter starts from 011, 010, 001 and 111, 110, 101. ld(ld)) ĭown counter Test Bench module down_counter_tb Modified D-flip flop module modified_d_flip_flop(q,q_bar,d1,d2,clk,ld when q=8'b00000000, ld=1 and sets counter output q=d2 and next cycle, ld=0 and takes d1 value. Here d2 stores the initial input values, and ld is being used as switch, i.e. When ld=0, output of d-flip flop q=d1 and q_bar=~d1 Task: Designing a 8-bit downcounter which takes an initial input value and start the downcount, and when count becomes 8'b0000_0000, it should automatically set to input value.Įx: If given input is 8'b10010100, counter should start counting down, when value reaches 8'00000000, it should automatically reset to 8'b10010100, and again start downcount repeatedly.įor this had written a modified D flip flop using behavioral method, which works as follows: ![]()
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